Conventional static random access memory (SRAM) arrays include a differential sense amplifier for determining the resulting voltage difference between a bitline and bitline bar of a column of SRAMs. However, the differential sense amplifier is sensitive to process variations especially as the speed of accessing the SRAMs memory array increases. As a result, high speed embedded SRAMs in current processors are not keeping pace with processor speeds in general. As such, as processor designs increase in scalability, the speed of the embedded cache SRAMs negatively limit the overall speed of the processor.